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TCA6424A
SCPS193C – JULY 2010 – REVISED APRIL 2014
TCA6424A Low-Voltage 24-Bit I2C and SMBus I/O Expander
With Interrupt Output, Reset, and Configuration Registers
1 Features
2 Description
•
This 24-bit I/O expander for the two-line bidirectional
bus (I2C) is designed to provide general-purpose
remote I/O expansion for most microcontroller
families via the I2C interface [serial clock (SCL) and
serial data (SDA)].
•
•
DEVICE NAME
TCA6424A
PACKAGE
BODY SIZE
UQFN (32)
5mm × 5mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
P04
P05
P06
P07
5
7
8
4
6
P02
P03
3
P00
P01
1
2
RGJ/RSM PACKAGE
(BOTTOM VIEW)
INT
VCCI
32
9
P10
31
10
P11
SDA
30
11
P12
SCL
29
12
P13
RESET
VCCP
28
13
P14
27
14
P15
ADDR
26
15
P16
GND
25
16
P17
22
21
20
19
18
17
P25
P24
P23
P22
P21
P20
Exposed
Center Pad
23
•
•
•
•
•
•
•
•
•
•
•
Device Information(1)
24
•
•
•
The major benefit of this device is its wide VCC range.
It can operate from 1.65 V to 5.5 V on the P-port side
and on the SDA/SCL side. This allows the TCA6424A
to interface with next-generation microprocessors and
microcontrollers on the SDA/SCL side, where supply
levels are dropping down to conserve power. In
contrast to the dropping power supplies of
microprocessors and microcontrollers, some PCB
components, such as LEDs, remain at a 5-V power
supply.
P26
•
Operating Power-Supply Voltage Range of 1.65 V
to 5.5 V
Allows Bidirectional Voltage-Level Translation and
GPIO Expansion Between:
– 1.8-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
– 2.5-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
– 3.3-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
– 5-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
I2C to Parallel Port Expander
Low Standby Current Consumption of 1 μA
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at
the SCL and SDA Inputs
– Vhys = 0.18 V Typ at 1.8 V
– Vhys = 0.25 V Typ at 2.5 V
– Vhys = 0.33 V Typ at 3.3 V
– Vhys = 0.5 V Typ at 5 V
5-V Tolerant I/O Ports
Active-Low Reset Input (RESET)
Open-Drain Active-Low Interrupt Output (INT)
400-kHz Fast I2C Bus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
P27
1
If used, the exposed center pad must be
connected as a secondary ground or left
electrically open.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA6424A
SCPS193C – JULY 2010 – REVISED APRIL 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
7
7
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Programming...........................................................
Register Maps .........................................................
15
16
17
19
22
Applications and Implementation ...................... 25
9.1 Typical Application .................................................. 25
10 Power Supply Recommendation ....................... 27
11 Device and Documentation Support ................. 29
11.1 Trademarks ........................................................... 29
11.2 Electrostatic Discharge Caution ............................ 29
11.3 Glossary ................................................................ 29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
3 Revision History
Changes from Revision B (September 2010) to Revision C
Page
•
Removed hard coded ordering information table. ................................................................................................................. 1
•
Updated document formatting. .............................................................................................................................................. 1
Changes from Revision A (August 2010) to Revision B
•
Revised document to updated document status from preview to production data. ............................................................... 1
Changes from Original (July 2010) to Revision A
•
2
Page
Page
Changed Recommended Supply Sequencing and Rates Table .......................................................................................... 27
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SCPS193C – JULY 2010 – REVISED APRIL 2014
4 Description (continued)
The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage
level on the P-port of the TCA6424A is determined by the VCCP.
The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted
with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the TCA6424A in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6424A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6424A can remain a simple slave device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to
share the same I2C bus or SMBus.
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TCA6424A
SCPS193C – JULY 2010 – REVISED APRIL 2014
www.ti.com
5 Pin Configuration and Functions
P04
P05
P06
P07
5
6
7
8
P02
P03
3
4
P00
P01
1
2
RGJ/RSM PACKAGE
(BOTTOM VIEW)
INT
VCCI
32
9
P10
31
10
P11
SDA
30
11
P12
SCL
29
12
P13
RESET
VCCP
28
13
P14
27
14
P15
ADDR
26
15
P16
GND
25
16
P17
20
19
P23
P22
18
21
17
22
P25
P24
P21
23
P26
P20
24
P27
Exposed
Center Pad
If used, the exposed center pad must be connected as a secondary ground or left electrically open.
Pin Functions
PIN
4
DESCRIPTION
PIN NO.
NAME
1
P00
P-port input/output (push-pull design structure). At power on, P00 is configured as an input.
2
P01
P-port input/output (push-pull design structure). At power on, P01 is configured as an input.
3
P02
P-port input/output (push-pull design structure). At power on, P02 is configured as an input.
4
P03
P-port input/output (push-pull design structure). At power on, P03 is configured as an input.
5
P04
P-port input/output (push-pull design structure). At power on, P04 is configured as an input.
6
P05
P-port input/output (push-pull design structure). At power on, P05 is configured as an input.
7
P06
P-port input/output (push-pull design structure). At power on, P06 is configured as an input.
8
P07
P-port input/output (push-pull design structure). At power on, P07 is configured as an input.
9
P10
P-port input/output (push-pull design structure). At power on, P10 is configured as an input.
10
P11
P-port input/output (push-pull design structure). At power on, P11 is configured as an input.
11
P12
P-port input/output (push-pull design structure). At power on, P12 is configured as an input.
12
P13
P-port input/output (push-pull design structure). At power on, P13 is configured as an input.
13
P14
P-port input/output (push-pull design structure). At power on, P14 is configured as an input.
14
P15
P-port input/output (push-pull design structure). At power on, P15 is configured as an input.
15
P16
P-port input/output (push-pull design structure). At power on, P16 is configured as an input.
16
P17
P-port input/output (push-pull design structure). At power on, P17 is configured as an input.
17
P20
P-port input/output (push-pull design structure). At power on, P20 is configured as an input.
18
P21
P-port input/output (push-pull design structure). At power on, P21 is configured as an input.
19
P22
P-port input/output (push-pull design structure). At power on, P22 is configured as an input.
20
P23
P-port input/output (push-pull design structure). At power on, P23 is configured as an input.
21
P24
P-port input/output (push-pull design structure). At power on, P24 is configured as an input.
22
P25
P-port input/output (push-pull design structure). At power on, P25 is configured as an input.
23
P26
P-port input/output (push-pull design structure). At power on, P26 is configured as an input.
24
P27
P-port input/output (push-pull design structure). At power on, P27 is configured as an input.
25
GND
Ground
26
ADDR
Address input. Connect directly to VCCP or ground.
27
VCCP
Supply voltage of TCA6424A for P port
28
RESET
Active-low reset input. Connect to VCCI through a pullup resistor, if no active connection is used.
29
SCL
Serial clock bus. Connect to VCCI through a pullup resistor.
30
SDA
Serial data bus. Connect to VCCI through a pullup resistor.
31
VCCI
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides voltage-level
translation.
32
INT
Interrupt output. Connect to VCCI through a pullup resistor.
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SCPS193C – JULY 2010 – REVISED APRIL 2014
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCCI
Supply voltage range
–0.5
6.5
V
VCCP
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Output voltage range (2)
–0.5
6.5
V
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
P port
VO < 0 or VO > VCCP
±20
SDA
VO < 0 or VO > VCCI
±20
P port
VO = 0 to VCCP
25
SDA, INT
VO = 0 to VCCI
15
P port
VO = 0 to VCCP
25
IIOK
Input/output clamp current
IOL
Continuous output low current
IOH
Continuous output high current
ICC
(2)
(3)
200
Continuous current through VCCP
160
Continuous current through VCCI
10
Package thermal impedance (3)
θJA
(1)
Continuous current through GND
RGJ package
50.05
RSM package
TBD
UNIT
mA
mA
mA
mA
°C/W
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2
kV
Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2)
0
01
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2000 V
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 2000 V
may actually have higher performance.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
VCCI
Supply voltage
1.65
5.5
V
VCCP
Supply voltage
1.65
5.5
V
0.7 × VCCI
VCCI
RESET
0.7 × VCCI
5.5
ADDR, P27–P00
0.7 × VCCP
5.5
SCL, SDA, RESET
–0.5
0.3 × VCCI
ADDR, P27–P00
–0.5
0.3 × VCCP
SCL, SDA
VIH
High-level input voltage
V
VIL
Low-level input voltage
IOH
High-level output current
P27–P00
10
mA
IOL
Low-level output current
P27–P00
25
mA
TA
Operating free-air temperature
85
°C
–40
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5
TCA6424A
SCPS193C – JULY 2010 – REVISED APRIL 2014
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6.4 Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
MIN
–1.2
VIK
Input diode clamp
voltage
II = –18 mA
1.65 V to 5.5 V
VPOR
Power-on reset voltage
VI = VCCP or GND, IO = 0
1.65 V to 5.5 V
IOH = –8 mA
P-port high-level output
voltage
VOH
IOH = –10 mA
IOL = 8mA
P-port low-level output
voltage
VOL
IOL = 10 mA
TYP (1)
1.2
2.3 V
1.8
3V
2.6
4.5 V
4.1
1.65 V
1
2.3 V
1.7
3V
2.5
4.5 V
4.0
1.65 V
0.45
2.3 V
0.25
3V
0.25
4.5 V
0.23
1.65 V
0.6
2.3 V
0.3
3V
0.25
VOL = 0.4 V
1.65 V to 5.5 V
3
INT
VOL = 0.4 V
1.65 V to 5.5 V
3
SCL, SDA, RESET
VI = VCCI or GND
ADDR
VI = VCCP or GND
IIH
P port
VI = VCCP
IIL
P port
VI = GND
ICC
(ICCP + ICCI)
Standby
mode
1
μA
30
SDA,
P port,
ADDR,
RESET
VI on SDA and RESET= VCCI
or GND,
VI on P port and ADDR =
VCCP,
IO = 0, I/O = inputs,
fSCL = 100 kHz
1.65 V to 5.5 V
1.7
10
SCL,
SDA,
P port,
ADDR,
RESET
VI on SCL, SDA and RESET =
VCCI or GND,
VI on P port and ADDR =
VCCP,
IO = 0, I/O = inputs,
fSCL = 0
1.65 V to 5.5 V
0.1
3
SCL,SDA
RESET
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
P port,
ADDR,
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
VI = VCCI or GND
SDA
VIO = VCCI or GND
P port
VIO = VCCP or GND
6
μA
8
SCL
μA
1
1.65 V to 5.5 V
CI
(1)
±0.1
SDA,
P port,
ADDR,
RESET
ΔICCP
Cio
±0.1
1.65 V to 5.5 V
1.65 V to 5.5 V
Additional
current in
Standby
mode
ΔICCI
V
mA
15
VI on SDA and RESET= VCCI
or GND,
VI on P port and ADDR =
VCCP,
IO = 0, I/O = inputs,
fSCL = 400 kHz
Operating
mode
V
0.24
SDA
II
1.4
V
4.5 V
IOL
UNIT
V
1
1.65 V
MAX
μA
25
μA
1.65 V to 5.5 V
60
1.65 V to 5.5 V
1.65 V to 5.5 V
6
7
7
8
7.5
8.5
pF
pF
Except for ICC, all typical values are at nominal supply voltage (VCCP = VCCI =1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. For ICC, all
typical values are at VCCP = VCCI = 3.3 V and TA = 25°C.
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6.5 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
FAST MODE
I2C BUS
MAX
0
400
μs
1.3
0
50
0
250
50
100
0
kHz
μs
0.6
4.7
2
UNIT
MIN
ns
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb
(1)
300
ticf
I2C input fall time
300
20 + 0.1Cb
(1)
300
ns
tocf
I2C output fall time; 10 pF to 400 pF bus
300
20 + 0.1Cb
(1)
300
μs
tbuf
I2C bus free time between Stop and Start
4.7
1.3
μs
tsts
I2C Start or repeater Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeater Start condition hold time
4
0.6
μs
2
0
ns
μs
tsps
I C Stop condition setup time
tvd(data)
Valid data time; SCL low to SDA output valid
1
1
μs
tvd(ack)
Valid data time of ACK condition; ACK signal from SCL low to SDA
(out) low
1
1
μs
(1)
4
ns
0.6
Cb = total capacitance of one bus line in pF
6.6 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 17)
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
tW
Reset pulse duration
4
4
ns
tREC
Reset recovery time
0
0
ns
600
600
ns
tRESET Time to reset
(1)
(1)
Minimum time for SDA to become high or minimum time to wait before doing a START.
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 14)
PARAMETER
FROM
TO
STANDARD MODE
I2C BUS
MIN
P port
INT
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
4
μs
4
4
μs
400
400
ns
tIV
Interrupt valid time
4
tIR
Interrupt reset delay time
SCL
INT
tPV
Output data valid
SCL
P27–P00
tPS
Input data setup time
P port
SCL
0
0
ns
tPH
Input data hold time
P port
SCL
300
300
ns
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
100
80
Supply Current, ICC (µA)
Supply Current, ICC (µA)
9
fSCL = 400 kHz
All I/Os unloaded
90
VCC = 5 V
70
60
50
VCC = 3.3 V
40
30
VCC = 2.5 V
20
VCC = 1.8 V
10
0
-40
-15
10
VCC = 5 V
7
6
VCC = 3.3 V
5
VCC = 2.5 V
4
3
2
1
35
60
0
–40
85
VCC = 1.8 V
–15
10
35
60
85
Temperature, TA (°C)
Temperature, TA (°C)
Figure 1. Supply Current vs Temperature
Figure 2. Standby Supply Current vs Temperature
100
VCC = 1.8 V
18
80
Sink Current, ISINK (mA)
Supply Current, ICC (µA)
20
fSCL = 400 kHz
All I/Os unloaded
90
70
60
50
40
30
20
10
TA = –40°C
16
14
TA = 25°C
12
10
8
6
4
TA = 85°C
2
0
1.65 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Supply Voltage, VCC (V)
Output Low Voltage, VOL (V)
Figure 3. Supply Current vs Supply Voltage
Figure 4. I/O Sink Current vs Output Low Voltage
24
VCC = 3.3 V
45
TA = –40°C
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
50
VCC = 2.5 V
22
20
18
TA = 25°C
16
14
12
10
8
TA = 85°C
6
4
35
25
20
15
5
0.3
0.4
0.5
0.6
TA = 85°C
10
0
0.2
TA = 25°C
30
2
0.1
TA = –40°C
40
0
0
8
SCL = VCC
All I/Os unloaded
8
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
Figure 5. I/O Sink Current vs Output Low Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
50
Output Low Voltage, VOL (mV)
Sink Current, ISINK (mA)
400
VCC = 5 V
45
TA = –40°C
40
35
TA = 25°C
30
25
20
15
10
TA = 85°C
5
0
0.1
0
0.2
0.3
0.4
0.5
350
VCC = 5 V, ISINK = 10 mA
300
250
200
VCC = 1.8 V, ISINK = 10 mA
150
100
VCC = 5 V, ISINK = 1 mA
VCC = 1.8 V, ISINK = 1 mA
50
0
−40
−15
10
35
60
85
Output Low Voltage, VOL (V)
Temperature, TA (°C)
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Low Voltage vs Temperature
20
25
VCC = 2.5 V
TA = –40°C
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
VCC = 1.8 V
16
TA = 25°C
12
8
TA = 85°C
4
0
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
VCC – VOH (V)
0.3
0.4
0.5
0.6
0.7
VCC – VOH (V)
Figure 9. I/O Source Current vs Output High Voltage
Figure 10. I/O Source Current vs Output High Voltage
50
50
VCC = 3.3 V
TA = –40°C
40
35
TA = 25°C
30
VCC = 5 V
45
Source Current, ISOURCE (mA)
45
Source Current, ISOURCE (mA)
0.2
25
20
15
TA = 85°C
10
5
TA = –40°C
40
TA = 25°C
35
30
25
20
15
TA = 85°C
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.6 0.7
0.1
0.2
0.3
0.4
0.5
0.6
VCC – VOH (V)
VCC – VOH (V)
Figure 11. I/O Source Current vs Output High Voltage
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
5
VCC – VOH (V)
4
3
VCC = 1.8 V, ISOURCE = 10 mA
2
1
VCC = 5 V, ISOURCE = 10 mA
0
−40
−15
10
35
60
85
Temperature, TA (°C)
Figure 13. I/O High Voltage vs Temperature
10
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7 Parameter Measurement Information
VCCI
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
ticf
tbuf
tvd
tsp
tocf
tvd
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 14. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
AD
1 DR 1
A
1
2
3
4
5
6
A
7
8
Data 1
ACK
From Slave
Data From Port
Data 2
A
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 15. Interrupt Load Circuit and Voltage Waveforms
12
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Parameter Measurement Information (continued)
500 W
Pn
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P PORT LOAD CONFIGURATION
SCL
P0
A
P3
0.7 ´ VCCP
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 ´ VCCI
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 16. P-Port Load Circuit and Timing Waveforms
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Parameter Measurement Information (continued)
VCCI
R L = 1 kW
500 W
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 17. Reset Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
8.1.1 Voltage Translation
Table 1 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the
TCA6424A.
Table 1. Voltage Translation
VCCI (SDA AND SCL OF I2C MASTER)
(V)
VCCP (P PORT)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
1.8
5
2.5
1.8
2.5
2.5
2.5
3.3
2.5
5
3.3
1.8
3.3
2.5
3.3
3.3
3.3
5
5
1.8
5
2.5
5
3.3
5
5
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8.2 Functional Block Diagram
INT
ADDR
SCL
SDA
VCCI
VCCP
RESET
GND
32
Interrupt
Logic
LP Filter
26
29
30
2
Input
Filter
Shift
Register
I C Bus
Control
31
P27–P20
P17–P10
P07–P00
I/O Port
Write Pulse
Read Pulse
27
28
24 Bits
Power-On
Reset
25
A.
All I/Os are set to inputs at reset.
B.
Pin numbers shown are for the RGJ package.
Figure 18. Positive Logic
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCCP
Configuration
Register
D
Q
Q1
FF
Write Configuration
Pulse
CK Q
D
Q
FF
Write Pulse
P00 to P27
CK Q
Output
Port
Register
Q2
Input
Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
ESD Protection Diode
CK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
Figure 19. Simplified Schematic of P00 to P27
16
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8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.3.2 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 20). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 21).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 20).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 22). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 20. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 21. Bit Transfer
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Feature Description (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 22. Acknowledgment on the I2C Bus
18
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Feature Description (continued)
Table 2. Interface Definition
BYTE
I2C slave address
I/O data bus
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
H
ADDR
R/W
P07
P06
P05
P04
P03
P02
P01
P00
P17
P16
P15
P14
P13
P12
P11
P10
P27
P26
P25
P24
P23
P22
P21
P20
8.3.3 Device Address
The address of the TCA6424A is shown in Figure 23.
Slave Address
0
1
0
0
Fixed
0
AD
1 DR R/W
Programmable
Figure 23. TCA6424A Address
Table 3. Address Reference
ADDR
I2C BUS SLAVE ADDRESS
L
34 (decimal), 22 (hexadecimal)
H
35 (decimal), 23 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.4 Programming
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6424A in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6424A registers and
I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and
back up to the operating voltage for a power-reset cycle.
8.4.2 Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6424A registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to VCCI, if no active connection is used.
8.4.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
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Programming (continued)
The INT output has an open-drain structure and requires pullup resistor to VCCP or VCCI depending on the
application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6424A
then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP.
8.4.4 Bus Transactions
Data is exchanged between the master and TCA6424A through write and read commands.
8.4.4.1 Writes
Data is transmitted to the TCA6424A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 23 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The twelve registers within the TCA6424A are grouped into four different sets. The four sets of registers are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the next register in the group of 3 registers (see Figure 24 and Figure 25). For example, if the
first byte is send to Output Port 2 (register 6), the next byte is stored in Output Port 0 (register 4).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
0
S
1
0
0 0
1 AD
DR 0
A 0
0
0
0
0
Data to Port 0
1 0/1 0/1 A 0.7
R/W Acknowledge
From Slave
Start Condition
Data to Port 1
0.0 A 1.7
Data 0
Acknowledge
From Slave
Data 1
1.0 A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 24. Write to Output Port Register
SCL
1
2
3
4
5
6
7
8
9
1
2
3
Slave Address
SDA
S
0
1
0
Start Condition
0
0
4
5
6
7
8
9
1
A
0
0
0
R/W Acknowledge
From Slave
0
3
4
5
6
7
8
9
1
Data to Register
Command Byte
1 AD
DR 0
2
1 0/1 0/1 0/1 A MSB
Data 0
Acknowledge
From Slave
3
2
4
5
Data to Register
LSB A MSB
Data1
LSB A
P
Acknowledge
From Slave
Figure 25. Write to Configuration or Polarity Inversion Registers
8.4.4.2 Reads
The bus master first must send the TCA6424A address with the LSB set to a logic 0 (see Figure 23 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6424A (see Figure 26 and Figure 27).
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Programming (continued)
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Slave Address
S
0
0
1
0
0
Acknowledge
From Slave
Acknowledge
From Slave
1 AD
DR 0
Command Byte
A
R/W
A
S
Acknowledge
From Slave
Slave Address
0
1
0
0
0
1
AD 1
DR
Data
A MSB
LSB A
First Byte
R/W
At this moment, master transmitter
becomes master receiver, and
slave receiver becomes slave transmitter.
Data From Lower
or Upper Byte Acknowledge
of Register
From Master
Data From Upper
or Lower Byte No Acknowledge
of Register
From Master
MSB
Data
LSB NA P
Last Byte
Figure 26. Read From Register
SCL
1
2
3
4
5
6
7
8
9
I0.x
SDA
S 0 1 0 0 0 1
AD
DR
1 A
Data 1
R/W Acknowledge
From Slave
I1.x
A
Data 2
Acknowledge
From Master
I2.x
A
Data 3
Acknowledge
From Master
I0.x
A
Data 4
Acknowledge
From Master
1 P
No Acknowledge
From Master
Read From
Port 0
Data Into
Port 0
Read From
Port 1
Data Into
Port 1
INT
tiv
tir
Read From
Port 2
Data Into
Port 2
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 26).
C.
Auto-increment mode is enabled.
Figure 27. Read Input Port Register
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8.5 Register Maps
8.5.1 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6424A. Four bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register
can be written or read through the I2C bus. The command byte is sent only during a write transmission.
The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command
byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set
to logic 0.
If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to
program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1,
previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed
(refer to Table 5).
If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the
same register bank is read each time. During a write operation, data is written to the same register bank each
time.
Reserved command codes and command byte outside the range stated in the Command Byte table must not be
accessed for proper device functionality.
AI
B6
B5
B4
B3
B2
B1
B0
Figure 28. Control Register Bits
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Register Maps (continued)
Table 4. Command Byte
AI
B6
CONTROL REGISTER BITS
B5
B4
B3
B2
B1
B0
AUTOINCREMENT
STATE
COMMAND
BYTE
(HEX)
0
0
0
0
0
0
0
0
Disable
00
1
0
0
0
0
0
0
0
Enable
80
0
0
0
0
0
0
0
1
Disable
01
1
0
0
0
0
0
0
1
Enable
81
0
0
0
0
0
0
1
0
Disable
02
1
0
0
0
0
0
1
0
Enable
82
0
0
0
0
0
0
1
1
Disable
03
1
0
0
0
0
0
1
1
Enable
83
0
0
0
0
0
1
0
0
Disable
04
1
0
0
0
0
1
0
0
Enable
84
0
0
0
0
0
1
0
1
Disable
05
1
0
0
0
0
1
0
1
Enable
85
0
0
0
0
0
1
1
0
Disable
06
1
0
0
0
0
1
1
0
Enable
86
0
0
0
0
0
1
1
1
Disable
07
1
0
0
0
0
1
1
1
Enable
87
0
0
0
0
1
0
0
0
Disable
08
1
0
0
0
1
0
0
0
Enable
88
0
0
0
0
1
0
0
1
Disable
09
1
0
0
0
1
0
0
1
Enable
89
0
0
0
0
1
0
1
0
Disable
0A
1
0
0
0
1
0
1
0
Enable
8A
0
0
0
0
1
0
1
1
Disable
0B
1
0
0
0
1
0
1
1
Enable
8B
0
0
0
0
1
1
0
0
Disable
0C
1
0
0
0
1
1
0
0
Enable
8C
0
0
0
0
1
1
0
1
Disable
0D
1
0
0
0
1
1
0
1
Enable
8D
0
0
0
0
1
1
1
0
Disable
0E
1
0
0
0
1
1
1
0
Enable
8E
0
0
0
0
1
1
1
1
Disable
0F
1
0
0
0
1
1
1
1
Enable
8F
(1)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
Input Port 0
Read byte
xxxx xxxx (1)
Input Port 1
Read byte
xxxx xxxx (1)
Input Port 2
Read byte
xxxx xxxx (1)
Reserved
Reserved
Reserved
Output Port 0
Read/write
byte
1111 1111
Output Port 1
Read/write
byte
1111 1111
Output Port 2
Read/write
byte
1111 1111
Reserved
Reserved
Reserved
Polarity Inversion
Port 0
Read/write
byte
0000 0000
Polarity Inversion
Port 1
Read/write
byte
0000 0000
Polarity Inversion
Port 2
Read/write
byte
0000 0000
Reserved
Reserved
Reserved
Configuration Port 0
Read/write
byte
1111 1111
Configuration Port 1
Read/write
byte
1111 1111
Configuration Port 2
Read/write
byte
1111 1111
Reserved
Reserved
Reserved
Undefined
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8.5.2 Register Descriptions
The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether
the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes
to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before
a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input
Port register will be accessed next.
Table 5. Registers 0, 1 and 2 (Input Port Registers)
BIT
I-07
I-06
I-05
I-04
I-03
I-02
I-01
DEFAULT
X
X
X
X
X
X
X
I-00
X
BIT
I-17
I-16
I-15
I-14
I-13
I-12
I-11
I-10
DEFAULT
X
X
X
X
X
X
X
X
BIT
I-27
I-26
I-25
I-24
I-23
I-22
I-21
I-20
DEFAULT
X
X
X
X
X
X
X
X
The Output Port registers (registers 4, 5 and 6) shows the outgoing logic levels of the pins defined as outputs by
the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads
from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin
value.
Table 6. Registers 4, 5 and 6 (Output Port Registers)
BIT
O-07
O-06
O-05
O-04
O-03
O-02
O-01
DEFAULT
1
1
1
1
1
1
1
O-00
1
BIT
O-17
O-16
O-15
O-14
O-13
O-12
O-11
O-10
DEFAULT
1
1
1
1
1
1
1
1
BIT
O-27
O-26
O-25
O-24
O-23
O-22
O-21
O-20
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 8, 9 and 10) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 7. Registers 8, 9 and 10 (Polarity Inversion Registers)
BIT
P-07
P-06
P-05
P-04
P-03
P-02
P-01
P-00
DEFAULT
0
0
0
0
0
0
0
0
P-10
BIT
P-17
P-16
P-15
P-14
P-13
P-12
P-11
DEFAULT
0
0
0
0
0
0
0
0
BIT
P-27
P-26
P-25
P-24
P-23
P-22
P-21
P-20
DEFAULT
0
0
0
0
0
0
0
0
The Configuration registers (registers 12, 13 and 14) configure the direction of the I/O pins. If a bit in these
registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a
bit in these registers is cleared to 0, the corresponding port pin is enabled as an output.
Table 8. Registers 12, 13 and 14 (Configuration Registers)
24
BIT
C-07
C-06
C-05
C-04
C-03
C-02
C-01
DEFAULT
1
1
1
1
1
1
1
C-00
1
BIT
C-17
C-16
C-15
C-14
C-13
C-12
C-11
C-10
DEFAULT
1
1
1
1
1
1
1
1
BIT
C-27
C-26
C-25
C-24
C-23
C-22
C-21
C-20
DEFAULT
1
1
1
1
1
1
1
1
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SCPS193C – JULY 2010 – REVISED APRIL 2014
9 Applications and Implementation
9.1 Typical Application
Figure 29 shows an application in which the TCA6424A can be used.
VCCI VCCP
10 kW (´ 7)
VCCI
(1.8 V)
10 kW
VCC
10 kW 10 kW
31
10 kW
29
SCL
Master
Controller SDA
30
32
INT
GND
29
RESET
Status
Monitor
VCCI
SCL
27
VCCP
P00
ALARM
(see Note D)
Subsystem 1
(e.g., Alarm)
1
A
SDA
P01
INT
2
ENABLE
RESET
P02
TCA6424A
P03
P04
24
P05
P27
23
P06
P26
22
P07
P25
21
P10
P24
20
P11
P23
19
P12
P22
18
P13
P21
17
P14
P20
P15
26
ADDR
P16
P17
GND
B
3
4
5
6
7
8
9
10
Keypad
11
12
13
14
15
16
25
A.
Device address configured as 0100000 for this example.
B.
P00 and P02–P10 are configured as inputs.
C.
P01, P11–P17, and P20–P27 are configured as outputs.
D.
Resistors are required for inputs (on P port) that may float. If a driver to an input will not let the input float, a resistor is
not needed. Outputs (in the P port) do not need pullup resistors.
Figure 29. Typical Application
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Typical Application (continued)
9.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 29. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that
must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off.
Figure 30 shows a high-value resistor in parallel with the LED. Figure 31 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kW
VCC
Px
Figure 30. High-Value Resistor in Parallel With the LED
3.3 V
5V
LED
VCC
Px
Figure 31. Device Supplied by a Low Voltage
26
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10 Power Supply Recommendation
In the event of a glitch or data corruption, TCA6424A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 32 and Figure 33.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 32. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
VCC
Ramp-Up
Ramp-Down
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 33. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 9 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset.
Table 9. Recommended Supply Sequencing and Rates (1)
MAX
UNIT
tVCC_FT
Fall rate
PARAMETER
See Figure 32
1
100
ms
tVCC_RT
Rise rate
See Figure 32
0.01
100
ms
tVCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 32
40
μs
tVCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 33
40
μs
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 34
1.2
V
tVCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 34
10
μs
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on fising VCC
1.033
1.428
V
(1)
MIN
TYP
TA = –40°C to 85°C (unless otherwise noted)
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 34 and Table 9 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 34. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 35 and Table 9 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 35. VPOR
28
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SCPS193C – JULY 2010 – REVISED APRIL 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA6424ARGJR
ACTIVE
UQFN
RGJ
32
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH424A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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